In conventional sub-micron designs, a multitude of components are integrated on System-on-Chip (SoC) products. These SoCs generally include one or more central processing units (CPUs) and associated memories, such as static random access memory (SRAM) or read only memory (ROM) in addition to several other components that are product and/or application specific.
In SoC designs, the size of embedded memory is typically in the order of megabytes. On processor-based SoC designs, cache and tightly coupled memories are commonplace. The current pace of memory technology has surpassed Moore's Law concerning the density and performance of integrated circuits by greater than a factor of two. Thus, in a typical SoC design, memories command a substantial amount of silicon, board real estate, and/or power. Further, the increasing demand for handheld devices, ranging from mobile phones to gaming devices, imposes a critical need for saving power.
Conventional memory technology includes power saving features, such as the so-called “light sleep,” “deep sleep,” and “shutdown” modes, each of which can be entered in response to providing an appropriate voltage level on a corresponding input of the memory device. For example, when a light sleep (LS) input on the memory device is active, the memory device will enter a low leakage mode, in which output pins on the memory device remain static. Similarly, when a deep sleep (DS) input on the memory device is active, power to the peripheral circuits of the memory device is removed, output pins of the memory device are pulled low, and contents of the memory device are retained in their current state. Likewise, when a shutdown (SD) input on the memory device is active, contents of the memory device are lost, and power is removed from peripheral circuits of the memory device and its core.
The on-chip memories (SRAM and ROM) are added to boost the performance of the CPU and thus the overall system. However, these memories, especially SRAMs, are usually large in size compared to ROM and consume a substantial amount of power, both in terms of dynamic and static power. Dynamic power is used to access memory by the CPU for operation of the on-chip devices. Thus, dynamic power is productive power. However, static power is technology dependent and has become very significant in sub-micron technology. Static power consumption is not productive and should be decreased. As a result, conventional memory devices generally provide various control options to decrease power consumption. Accordingly, these memories are referred to as power gated memories.
Standard power control modes include the light sleep (LS) mode, deep sleep (DS) mode, and shutdown (SD) mode. Typical input/output pins are shown in FIG. 1 for an SRAM 10. The various types of input pin include address (A), data (D), write enable (WE), chip select (CS), clock (CLK), light sleep (LS), deep sleep (DS), and shutdown (SD). The output pin type includes data (Q). The power consumption in each of these modes is less than that in an active mode when the memory device is fully functional. However, there is generally a significant difference in power consumption between these power saving modes. In general, power consumed in the LS mode is greater than power consumed in the DS mode, which is greater than power consumed in the SD mode due to the power control architecture of the memory device. The SD mode enables the greatest power saving, but results in data stored in the memory device being lost. Thus, the SD mode is used if the system is to stop operation completely. However, both LS and DS power modes allow the memory device to retain data and are thus very useful when the CPU and/or system is idle or in sleep mode since these modes permit resumption of normal operation without reloading the contents of memory.